This application claims priority based on Korean Patent Application No. 2003-49548, filed on Jul. 19, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a structure for preventing the level of a boosting voltage applied to a node from dropping.
2. Discussion of Related Art
A semiconductor memory device has various internal power voltage levels. In particular, a boosting power voltage (VPP) level is higher than a general power voltage (VDD) level and is considered to be at a negative voltage level (VBB) when lower than a ground voltage (VSS).
However, it is quite difficult to increase driving capability while the boosting power voltage (VPP or VBB) level is maintained. Also, the boosting power voltage (VPP or VBB) level may require an increase in size of a semiconductor chip.
In a semiconductor memory device, a specific node to which a boosting power voltage (VPP or VBB) is applied is electrically connected to another node. As a result, the level of the boosting power voltage (VPP or VBB) of the specific node may drop due to fine particles.
A memory cell array with a relatively large area is greatly affected by the fine particles. For example, output lines of a row decoder are formed of metal layers over the memory cell array and are connected to a sub word line driver including a p-channel metal-oxide semiconductor (PMOS) transistor. The output lines of the row decoder are at a boosting power voltage (VPP) level, and at a negative boosting voltage (VBB) level in a negative word line source scheme. When the output lines of the row decoder are at the negative boosting voltage (VBB) level, a bridge is formed between the output lines and a cell plate under the output lines due to fine particles. Thus, stand-by current increases, and the negative boosting voltage (VBB) level increases to the same voltage level as the cell plate. As a result, the semiconductor chip may exhibit a defect.
FIG. 1 is a schematic view of an array signal structure according to a conventional semiconductor memory device. Referring to FIG. 1, a semiconductor memory device 100 includes a memory cell array block (MCAB), a sense amplifier (S/A) block, a row decoder 110, and a column decoder 120.
The row decoder 110 outputs a normal word line enable (NWE) signal to a sub word line driver (SWD). The SWD outputs the NWE signal to a lower layer or an active area via a metal contact (MC), a direct contact (DC), or the like.
The NWE signal is transmitted via output lines RDOUT of the row decoder 110. The output lines RDOUT of the row decoder 110 are first metal layers.
In the S/A block, the column decoder 120 outputs a column select line (CSL) signal to the first metal layers via a via contact (VC) and to a column select line transistor (not shown) via the MC, DC, or the like.
The CSL signal is transmitted via output lines CDOUT of the column decoder 120. The output lines CDOUT of the column decoder 120 are second metal layers.
The output lines RDOUT of the row decoder 110 in the semiconductor memory device 100 are the first metal layers, and the output lines CDOUT of the column decoder 120 are the second metal layers. Also, the first metal layers are orthogonal to the second metal layers.
The second metal layers are disposed over the first metal layers. Thus, the output lines CDOUT of the column decoder 120 are disposed over the output lines RDOUT of the row decoder 110 in the MCAB or the S/A block.
FIG. 2 is a side view of an array signal structure according to the conventional semiconductor memory device shown in FIG. 1.
As shown in FIG. 2, the semiconductor memory device 100 includes storage-poly silicon (S_POLY), which is connected to an active area ACTIVE and is a component of a storage cell, and plate-poly silicon (P_POLY) which is a component of a cell capacitor.
Output lines RDOUT of a row decoder are first metal layers MT1 and are disposed over the plate-poly silicon P_POLY. Output lines CDOUT of a column decoder are second metal layers MT2 and are disposed over the first metal layers MT1 in an orthogonal direction.
The plate-poly silicon P_POLY encloses the entire storage-poly silicon S_POLY and generally has a half voltage level (½VCC) of a high level of data, which is the highest potential of the storage cell, to reduce an electric field of the cell capacitor.
As previously described, the output lines RDOUT of the row decoder are at a negative boost voltage (VBB) level in the negative word line source scheme.
However, since the output lines RDOUT of the row decoder, which are the first metal layers MT1, are disposed adjacent to the plate-poly silicon P_POLY, an electric bridge is formed between the output lines RDOUT of the row decoder and the plate-poly silicon P_POLY due to fine particles existing between the output lines RDOUT and the plate-poly silicon P_POLY.
Due to the electric bridge, stand-by current increases and the negative boosting voltage (VBB) level of the output lines RDOUT of the row decoder increases to the voltage level of the plate-poly silicon P_POLY. As a result, the semiconductor memory device 100 exhibits a defect.